The invention relates to buffers and, more particularly, to a voltage clamp for a buffer in an electronic device, the buffer presenting a high impedance when the electronic device is in an inoperable state and clamping a voltage present at the output terminal of the buffer when the electronic device is in an operable state.
A buffer provides an interface between a first electronic device which typically includes the buffer, and a network, second electronic device, or a plurality of other devices. For example, a buffer may be provided in a printer that connects to a network which has a plurality of computers or other electronic devices connected thereto. Loss of power or failure of an electronic device cannot adversely affect operation of other electronic devices connected to the inoperable electronic device. A failsafe buffer presents a high impedance to other electronic devices connected to the network when an electronic device including a failsafe buffer is powered-off or otherwise is rendered inoperable. Thus, a failsafe buffer does not affect operation of other devices on the network when the electronic device including the failsafe buffer fails, is powered-off, or is otherwise caused to be inoperable.
CMOS buffers generally include a P-channel transistor connected between the buffer power supply, VDD, and the output terminal, and a N-channel transistor connected between the output terminal and ground. The N-tub, which comprises the back gate of the P-channel transistor is typically connected directly to the power supply. Consequently, the parasitic diode formed between the P+ source and the N-tub of the P-channel will clamp any voltage at the output terminal of the buffer to a voltage approximately equal to VDD plus one diode voltage drop. In a failsafe buffer, however, connection to the parasitic diode is not permitted because loss of VDD would cause signals present at the output terminal to be clamped at 0.6 V. This result is clearly unacceptable.
However, it is desirable to include a clamp at the buffer output to reduce ringing (e.g., extraneous voltages, reflected signals, etc.) that may adversely affect operation of the electronic device within which the failsafe buffer is provided.
It is thus desirable to provide a voltage clamp for a failsafe buffer in an electronic device that clamps a voltage present at the output terminal of the buffer only when the electronic device is powered-on, i.e., only when VDD is present, and does not affect operation of other electronic devices when the electronic device is powered-off or otherwise rendered inoperable.
The present invention is directed to a failsafe buffer for an electronic device. The buffer includes an output terminal and means for clamping a voltage present at the output terminal to a predetermined voltage when the electronic device is in an operable state.
The present invention is also directed to a voltage clamp for a failsafe buffer having an output terminal and being connected to a power source for providing a voltage to the buffer. The voltage clamp comprises a plurality of serially connected switches operable in response to the power source such that a voltage present at the output terminal is limited to a first predetermined voltage when the power source provides a second predetermined voltage to the buffer.
The present invention is further directed to an electronic device comprising a power source for providing an operating voltage to the device. An operable state of the device is defined when the power source provides a first predetermined operating voltage to the device. The electronic device also includes a failsafe buffer having an output terminal and including a voltage clamp operable in response to the power source for clamping a voltage present at the output terminal to a predetermined voltage when the electronic device is in the operable state.